Title :
Implementation of technology scaling on leakage reduction techniques using cadence tools with 45 nm technology
Author :
Akashe, Shyam ; Bhushan, Sushi ; Sharma, Sanjay
Author_Institution :
Inst. of Technol. & Manage., Gwalior, India
Abstract :
The impact of technology scaling on three run-time leakage reduction techniques (Input Vector Control, Body Bias Control and Power Supply Gating) is evaluated by determining limits and benefits, in terms of the potential leakage reduction, performance penalty, and area and power overhead in 180nm, 90nm, and 45nm technologies. Cadence simulation results and estimations with various functional units and memory structures are presented to support a comprehensive analysis.
Keywords :
SRAM chips; circuit simulation; integrated circuit design; power supply circuits; Cadence simulation tool; SRAM array; body bias control; functional units; input vector control; memory structures; power supply gating; run-time leakage reduction techniques; size 180 nm; size 45 nm; size 90 nm; technology scaling; Logic gates; Leakage reduction; low power; technology scaling;
Conference_Titel :
Nanoscience, Engineering and Technology (ICONSET), 2011 International Conference on
Conference_Location :
Chennai
Print_ISBN :
978-1-4673-0071-1
DOI :
10.1109/ICONSET.2011.6167912
