DocumentCode :
3534447
Title :
Design and performance evaluation of Hybrid Prefix Adder and carry increment adder in 90nm regime
Author :
Nagamani, A.N. ; Shivanand, B.K.
Author_Institution :
PES Inst. of Technol., Bangalore, India
fYear :
2011
fDate :
28-30 Nov. 2011
Firstpage :
198
Lastpage :
201
Abstract :
This paper presents an implementation of two 8-bit adders (HPA and CIA) and comparing their performance with respect to power delay product for different voltages in 90 nm regime. HPA is derived from Parallel prefix adders for minimized Power Delay product. CIA is derived from carry select adder with reduced area scheme for carry-select adders lowers this overhead by computing the carry and sum bits for a block-carry-in value of 0 only and by incrementing them afterwards depending on the final block-carryin. For 8-bit implementation of carry generation, HPA needs 158 transistors where as CIA needs 282 transistors. HPA gives reduced power delay product compared to CIA. Tanner EDA tool is used for schematic implementation and simulating the adder designs in the 90 nm technology.
Keywords :
adders; Tanner EDA tool; adder designs; block-carry-in value; carry generation; carry increment adder; carry select adder; hybrid prefix adder; performance evaluation; power delay product reduction; reduced area scheme; size 90 nm; word length 8 bit; Delay; Area efficient; CIA -Carry Increment Adder; HPA -Hybrid Prefix Adder; Power Delay Product;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Nanoscience, Engineering and Technology (ICONSET), 2011 International Conference on
Conference_Location :
Chennai
Print_ISBN :
978-1-4673-0071-1
Type :
conf
DOI :
10.1109/ICONSET.2011.6167953
Filename :
6167953
Link To Document :
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