A design flow for linear-phase fixed-point FIR filters: from the NPRM specifications to a VHDL code

This work combines two distinct research efforts, the coefficient design and the adder-number reduction, of fixed-point FIR filters into an automatic design flow. Given the normalized peak-ripple-magnitude (NPRM) specifications, the canonic-signed-digit (CSD) filter coefficients are calculated by the partial mixed-integer-linear-programming (PMILP) algorithm. Then a signed common subexpression sharing (SCSS) algorithm is used to reduce the number of adders required to implement the FIR filter. Finally a VHDL code that describes the FIR filter hardware with SCSS is generated.