Logic design for low-power CMOS circuits

Author

Piguet, C.

Author_Institution

Centre Suisse d´´Electronique et de Microtechnique SA, Neuchatel, Switzerland

fYear

1995

fDate

6-10 Nov 1995

Firstpage

299

Lastpage

302

Abstract

This paper presents the design of low-voltage and low-power CMOS circuits. It is based on a branch-based logic style that provides many benefits. Branch-based logic is presented and compared to other logic styles. Race-free flip-flops as well as complex gate decomposition are introduced and discussed from the low-voltage/low-power point of view. The advantages of branch modelization compared to cell modelization are presented. Logic parallelization used for some basic cell and logic modules such as shift registers is presented

Keywords

CMOS logic circuits; application specific integrated circuits; flip-flops; integrated circuit design; logic design; ASIC design; branch modelization; branch-based logic style; complex gate decomposition; logic design; logic parallelization; low-power CMOS circuits; low-voltage circuits; race-free flip-flops; shift registers; CMOS logic circuits; Energy consumption; Flip-flops; Libraries; Logic design; Logic devices; Logic gates; Low voltage; Parasitic capacitance; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronics and VLSI, 1995. TENCON '95., IEEE Region 10 International Conference on

Print_ISBN

0-7803-2624-5

Type

conf

DOI

10.1109/TENCON.1995.496399

Filename

496399

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3536635