A new incremental simulation algorithm for large scale circuits and its evaluation

The incremental simulation algorithm speeds up the simulation of digital hardware by storing and reusing simulation events. For large circuits, in order to reduce the amount of events to be stored, it is necessary to select nets and store only the events relevant to those nets. Our new incremental simulation algorithm selects nets according to expected amounts of evaluation eliminated by storing each net´s simulation events. Compared to traditional net selection algorithms, speedups of 1.78 to 1.94 were achievable with our algorithm