Low hardware complexity parallel turbo decoder architecture

Turbo decoders inherently have low throughput and long latency because of iterative decoding. Parallel processing is a powerful technique for high-throughput applications but often comes with large hardware complexity penalties. In this paper, we present a generic low hardware complexity parallel turbo decoder architecture, which enables multiple soft-input soft-output (SISO) decoders to process one data frame simultaneously. It can achieve multiple times the throughput of a typical serial decoder with a small fraction of hardware overhead. The proposed architecture works for any type of random interleavers, which makes it extremely useful in practical applications where turbo interleave patterns are not free to design. Based on estimation, the illustrated low hardware complexity 2-level parallel turbo decoding architecture can achieve twice the throughput of a typical serial decoding architecture with less than 20% hardware overhead when applied to 3rd generation CDMA systems.