Title :
VLSI implementation of multiprocessor system
Author :
Kang, Jun-Woo ; Rim, Kee-Wook
Author_Institution :
Syst. Res. Dept., Electron. & Telecommun. Res. Inst., Daejeon, South Korea
Abstract :
Integrating multiple processors into a chip is one of the leading technologies in computer architecture. This paper describes EMPC-96 which is an on-chip multiprocessor with shared cache architecture. Four integer units, data cache, instruction cache, dispatcher, and system interfaces are integrated into single chip. 400 MIPS is a target of the performance of this design
Keywords :
VLSI; microprocessor chips; multiprocessing systems; parallel architectures; 400 MIPS; EMPC-96; VLSI; computer architecture; data cache; dispatcher; instruction cache; integer units; microprocessors; on-chip multiprocessor; shared cache architecture; single chip integration; system interfaces; Computer architecture; Fabrication; Independent component analysis; Microprocessors; Multiprocessing systems; Pipelines; System-on-a-chip; Tellurium; VLIW; Very large scale integration;
Conference_Titel :
Microelectronics and VLSI, 1995. TENCON '95., IEEE Region 10 International Conference on
Print_ISBN :
0-7803-2624-5
DOI :
10.1109/TENCON.1995.496445
