VLSI architecture for real-time fractal video encoding

A very low bit-rate video coding scheme with fixed-block-size full-search fractal (FFF) coding and DCT has recently been proposed. In this paper, we introduce an efficient systolic array for FFF coding algorithm. By fully utilizing the data dependency, the proposed architecture can achieve high throughput and thus can deliver very low bit-rate video (QCIF) in real time. By estimating the number of required gates, the proposed architecture can be implemented in a single chip with the state-of-the-art VLSI technology. Therefore, a cost effective VLSI implementation can be achieved