DocumentCode
3540764
Title
A 32×24-bit multiplier-accumulator with advanced rectangular styled Wallace-tree structure
Author
Itoh, Niichi ; Tsukamoto, Yasumasa ; Shibagaki, Takeshi ; Nii, Kouji ; Takata, Hidehiro ; Makino, Hiroshi
Author_Institution
Renesas Technol. Corp., LSI Technol. Unit, Hyogo, Japan
fYear
2005
fDate
23-26 May 2005
Firstpage
73
Abstract
We introduce the advanced rectangular styled Wallace-tree construction method. This method realizes a compact layout and high-speed operation of multiplier. A 32×24-bit multiplier-accumulator was constructed using this new method. 540 um×840 um area size and 300 MHz clock speed were achieved using 0.15 um CMOS logic process technology with flash memory.
Keywords
CMOS logic circuits; carry logic; digital circuits; logic circuits; 0.15 micron; 300 MHz; CMOS logic process; compact layout; flash memory; high-speed operation; multiplier-accumulator; rectangular styled Wallace-tree structure; Adders; CMOS logic circuits; CMOS process; CMOS technology; Clocks; Degradation; Flash memory; Large scale integration; Microcontrollers; Ubiquitous computing;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on
Print_ISBN
0-7803-8834-8
Type
conf
DOI
10.1109/ISCAS.2005.1464527
Filename
1464527
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