ANTICS analogue fault simulation software

The increasing size and complexity of analogue and mixed signal ICs combined with market pressures of increased quality levels and reduced cost has led to an interest in structural test methods for analogue and mixed-signal ICs. The aim of such tests is to verify the integrity of the circuit by detecting manufacturing defects directly, rather than through the resultant functional specification error. In order to quantify the effectiveness of a structural test through simulation, manufacturing defects are represented using simulation fault models. By comparing the simulation output from a fault-free circuit and that of a circuit with a simulation fault model injected into it, a measure of the detectability of a fault for a given structural test can be obtained. This is the principle of the ANTICS analogue fault simulation software which is described in this paper