A combined two´s complement and floating-point comparator

This paper presents the design of a combined two´s complement and IEEE 754-compliant floating-point comparator. Unlike previous designs, this comparator incorporates both operand types into one unit, while still maintaining low area and high speed. The comparator design uses a novel magnitude comparator with logarithmic delay, plus additional logic to handle both two´s complement and floating point operands. The comparator fully supports 32-bit and 64-bit floating-point comparisons, as defined in the IEEE 754 standard, as well as 32-bit and 64-bit two´s complement comparisons. Area and delay estimates are presented for designs implemented in AMI C5N 0.5 μm CMOS technology.