Optimum quiescent point of integrated power CMOS transistor for wireless portable applications

Author

Hsu, Heng-Ming ; Lee, Tai-Hsing

Author_Institution

Dept. of Electr. Eng., Nat. Chung-Hsing Univ., Taichung, Taiwan

fYear

2005

fDate

23-26 May 2005

Firstpage

129

Abstract

According to the proposed silicon integrated power MOS transistor by adopting 0.18 μm technology, the performance shows this novel device can be operated at 2.4GHz for Bluetooth applications. After optimization of quiescent point by executing the matrix measurement of large-signal characteristic, the maximum output power is 21.26dBm corresponding to power added efficiency of 44.3%. Therefore, this device can provide portable handhelds with the properties of short-distance, low-power, and high-frequency operation.

Keywords

Bluetooth; CMOS integrated circuits; circuit optimisation; low-power electronics; mobile handsets; power integrated circuits; 0.18 micron; 2.4 GHz; 44.3 percent; Bluetooth applications; CMOS transistor; high-frequency operation; large-signal characteristic; low-power operation; matrix measurement; optimization; optimum quiescent point; portable handhelds; short-distance operation; silicon integrated power MOS transistor; wireless portable applications; Bluetooth; CMOS technology; Cutoff frequency; MOSFETs; Power generation; Power measurement; Power transistors; Radio frequency; Silicon; Voltage; 20dBm output power; Bluetooth; Optimum DC bias; Power CMOS transistor;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on

Print_ISBN

0-7803-8834-8

Type

conf

DOI

10.1109/ISCAS.2005.1464541

Filename

1464541