Title :
Quality considerations in delay fault testing
Author :
Pierzynska, Alicja ; Pilarski, Slawomir
Author_Institution :
Sch. of Comput. Sci., Simon Fraser Univ., Burnaby, BC, Canada
Abstract :
We examine delay model used in VLSI circuit testing. Our study includes electrical-level simulation experiments with HSPICE. We show phenomena which significantly affect the actual delays, but which are not taken into account by the existing model used in testing. Our analysis questions the test quality offered by test generation procedures used so far
Keywords :
CMOS logic circuits; SPICE; VLSI; circuit analysis computing; combinational circuits; delays; fault diagnosis; integrated circuit testing; logic CAD; logic design; logic testing; HSPICE; VLSI circuit testing; delay fault testing; electrical-level simulation experiments; quality considerations; test generation procedures; Circuit faults; Circuit testing; Delay estimation; Electrical fault detection; Fault detection; Logic circuits; Logic testing; Propagation delay; Semiconductor device modeling; Very large scale integration;
Conference_Titel :
Design Automation Conference, 1995, with EURO-VHDL, Proceedings EURO-DAC '95., European
Conference_Location :
Brighton
Print_ISBN :
0-8186-7156-4
DOI :
10.1109/EURDAC.1995.527408
