Controlled Ge nanowires growth on patterned Au catalyst substrate

One-dimensional semiconductor nanostructures have attracted much attention because of their potential applications in the design of novel electronic, photonic, and sensing devices. Due to their high mobility of electrons and holes, Ge nanowires are particularly attractive for high-speed field-effect transistors. Moreover, Ge nanowires are potentially useful for building quantum bits because of a long decoherence time due to a predominance of spin-zero nuclei and the advantage of a large excitonic Bohr radius (24.3 nm) which allows the quantum confinement to be observed for relatively large structures and at high temperatures. To realize these applications on a large scale, one of the key challenges is to develop a convenient and parallel method to align bottom-up nanowires into complex patterns or structures. Recently, a "pick and place" method is most widely used for integrating nanowires. However, these processes lack control in precision, repeatability, and easily induce contamination and defects in the wires. It is expected to selectively grow nanowires directly onto desired areas of the substrate and in situ fabricate the nanowire devices. In the VLS (vapor-liquid-solid) CVD process, gold catalysts initiate and guide the growth of nanowires. Hence, precise control the location of nanowires relies on the capability to control the location of Au clusters. In this paper, we demonstrate the well location-controllable Ge nanowires on SiO₂ substrate by combining top-down and bottom-up methods.