Title :
On-board fault-tolerant SAR processor for spaceborne imaging radar systems
Author :
Fang, Wai-Chi ; Le, Charles ; Taft, Stephanie
Author_Institution :
Jet Propulsion Lab., California Inst. of Technol., Pasadena, CA, USA
Abstract :
A real-time high-performance and fault-tolerant FPGA-based hardware architecture for the processing of synthetic aperture radar (SAR) images has been developed for advanced spaceborne radar imaging systems. In this paper, we present the integrated design approach, from top-level algorithm specifications, system architectures, design methodology, functional verification, performance validation, down to hardware design and implementation.
Keywords :
digital signal processing chips; fault tolerance; field programmable gate arrays; radar imaging; spaceborne radar; synthetic aperture radar; FPGA; SAR image processing; functional verification; on-board fault-tolerant SAR processor; performance validation; spaceborne imaging radar systems; synthetic aperture radar images; Computer architecture; Fault tolerant systems; Hardware; Laboratories; Radar imaging; Real time systems; Signal processing algorithms; Space technology; Spaceborne radar; Synthetic aperture radar;
Conference_Titel :
Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on
Print_ISBN :
0-7803-8834-8
DOI :
10.1109/ISCAS.2005.1464614
