Title :
Efficient VLSI implementation of N/N integer division
Author :
Khoo, Kei-Yong ; Willson, Alan N., Jr.
Author_Institution :
Cadence Design Syst., San Jose, CA, USA
Abstract :
The paper presents an efficient implementation of an N-bit by N-bit combinational divider using the nonrestoring shift-subtract algorithm. A theoretical speed-up of 50% for an N/N-bit divider, compared to a merely truncated array implementation, is demonstrated. In practice, delay reduction of 25%-35% can easily be achieved with very little area overhead.
Keywords :
VLSI; delays; digital arithmetic; digital signal processing chips; dividing circuits; integrated circuit design; VLSI implementation; combinational divider; digital signal processing algorithms; integer division; nonrestoring shift-subtract algorithm; truncated array implementation; Adders; Circuits; Difference equations; Logic; Propagation delay; Registers; Very large scale integration;
Conference_Titel :
Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on
Print_ISBN :
0-7803-8834-8
DOI :
10.1109/ISCAS.2005.1464677
