Title :
Statistical schedule length analysis in asynchronous datapath synthesis
Author :
Ohashi, Koji ; Kaneko, Mineo
Author_Institution :
Sch. of Inf. Sci., Japan Adv. Inst. of Sci. & Technol., Ishikawa, Japan
Abstract :
The paper proposes statistical schedule length analysis for evaluating schedule and datapath during asynchronous datapath synthesis. In order to handle the randomness of delay variation mathematically, the execution time of each operation is modeled by a stochastic variable, and an algorithm to calculate the distribution of total computation time of an application is presented. The proposed statistical schedule length analysis is then incorporated with resource binding and scheduling to form an asynchronous datapath synthesis system. Our system tends to generate better solutions than the conventional one in the mean total computation time, when the size of a target algorithm becomes larger, the number of functional units becomes larger, and the variance of execution delay of each module becomes larger. Experimental results have been obtained for a differential equation solver, a wave digital filter and elliptic wave filters.
Keywords :
VLSI; delays; digital signal processing chips; graph theory; logic design; processor scheduling; resource allocation; statistical analysis; stochastic processes; DSP chips; VLSI system; asynchronous datapath synthesis; combinatorial circuit; delay variation; dependence graph; digital circuit; digital signal processing; resource binding; resource sharing; scheduling graph; statistical schedule length analysis; stochastic variable; total computation time; Clocks; Data analysis; Delay effects; Distributed computing; Information science; Job shop scheduling; Processor scheduling; Scheduling algorithm; Statistical analysis; Stochastic processes;
Conference_Titel :
Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on
Print_ISBN :
0-7803-8834-8
DOI :
10.1109/ISCAS.2005.1464684