Title :
Decision feedback equalization for high-speed backplane data communications
Author :
Chen, Jing ; Li, Miao ; Kwasniewski, Tad
Author_Institution :
Dept. of Electron., Carleton Univ., Ottawa, Ont., Canada
Abstract :
The proposed 2 post-tap decision feedback equalizer (DFE) implementation consists of two equalizing amplifiers (summing nodes) connected to incoming data and feedback loops. Two parallel branches consisting of equalizing amplifier and two flip-flops each are also present and followed by a MUX. The design is verified by HSPICE using 0.18 μm CMOS process parameters. Simulation results show an increase of horizontal and vertical eye opening at data rates up to 8 Gbit/s. Data is transmitted over a 34" FR4 backplane with BER less than 10-15. The total power consumption is 12mW at a 1.8V supply.
Keywords :
CMOS integrated circuits; data communication; decision feedback equalisers; feedback amplifiers; flip-flops; summing circuits; 2 post-tap decision feedback equalizer; CMOS process; DFE; FR4 backplane; MUX; decision feedback equalization; equalizing amplifiers; eye opening; feedback loop; flip-flops; high-speed backplane data communications; incoming data loop; parallel branches; summing nodes; Backplanes; Bandwidth; Circuits; Clocks; Data communication; Decision feedback equalizers; Finite impulse response filter; Frequency; Intersymbol interference; Timing;
Conference_Titel :
Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on
Print_ISBN :
0-7803-8834-8
DOI :
10.1109/ISCAS.2005.1464827
