Title :
A low power decimation filter architecture for high-speed single-bit sigma-delta modulation
Author :
Gustafsson, Oscar ; Ohlsson, Henrik
Author_Institution :
Dept. of Electr. Eng., Linkoping Univ., Sweden
Abstract :
A novel architecture, suitable for high-speed FIR decimation filters for single-bit sigma-delta modulation, is proposed. By using efficient data and coefficient representation, the total number of partial products is reduced, leading to low power consumption. The work focuses on filters whose design is based on cascaded comb filters, although the approach is applicable to any FIR filter.
Keywords :
FIR filters; comb filters; distributed arithmetic; logic design; low-power electronics; power consumption; sigma-delta modulation; FIR decimation filters; analog-to-digital conversion; cascaded comb filters; coefficient representation; data representation; distributed arithmetic architecture; high-speed FIR filters; high-speed single-bit sigma-delta modulation; low power decimation filter architecture; partial products; power consumption; Analog-digital conversion; Arithmetic; Attenuation; Costs; Delta-sigma modulation; Electronic mail; Energy consumption; Finite impulse response filter; Interpolation; Power filters;
Conference_Titel :
Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on
Print_ISBN :
0-7803-8834-8
DOI :
10.1109/ISCAS.2005.1464872
