An MCML four-bit ripple-carry adder design in 1 GHz range

By introducing a mathematical programming technique, we detail the full-custom design of a minimum-delay four-bit ripple-carry adder (RCA). The technique may be used to achieve a variety of design goals, such as minimum delay, and minimum power-delay product (PDP). We demonstrate how to obtain practical circuits by deriving appropriate objective functions and imposing relevant constraints and design-variable ranges. The circuit is implemented in a standard 0.18 μm CMOS technology. Post-layout simulation verifies the functionality of our design and shows that our performance predictions are accurate within 15%. The total area of the MCML four-bit RCA is 3733.3 μm².