A 1.2V multi Gb/s/pin memory interface circuits with high linearity and low mismatch

This paper describes memory interface circuits applicable to multi Gbit/s/pin chip-to-chip communication. To obtain the high linearity characteristics of the off-chip drivers (OCD) and the on-die terminators (ODT), a novel circuit structure is proposed. The linearity error of the designed OCD and ODT is 4.7% and 1.7% respectively when measured between 0.2V and 1V. The pull-up and pull-down impedance mismatch is reduced by adding a compensation impedance unit. The maximum pull-up and pulldown mismatch is 0.5 bit. An impedance update scheme without training sequence is designed to guarantee the signal integrity of the first data. The valid data window is 418ps at 2Gbit/s, Vref ±150mV. The proposed circuits are fabricated with 0.1μm dual-oxide CMOS process technology.