• DocumentCode
    3544097
  • Title

    A 100×100 pixels orientation-selective multi-chip vision system

  • Author

    Shimonomura, Kazuhiro ; Yagi, Tetsuya

  • Author_Institution
    Graduate Sch. of Eng., Osaka Univ., Japan
  • fYear
    2005
  • fDate
    23-26 May 2005
  • Firstpage
    1915
  • Abstract
    We describe a multi-chip analog VLSI system which emulates the orientation selective response of the simple cell in the primary visual cortex. The system consists of two analog chips, a silicon retina and an orientation chip, which mimic the parallel and hierarchical architecture of the visual system in the brain. The spatial resolution of the system is 100×100 pixels. The silicon retina receives the input image with a Laplacian-Gaussian-like receptive field. The output image of the retina is transferred to the orientation selection chip. The image transmission between two chips is carried out using analog signals. The orientation chip selectively aggregates multiple pixels of the silicon retina, mimicking the feed-forward model proposed to explain the orientation-selective receptive field of the simple cell. The orientation chip provides three output images with different preferred orientation in parallel. The analog multi-chip architecture used in the present study is useful to mimic the responses of higher order cells in the primary visual cortex.
  • Keywords
    VLSI; computer vision; feedforward; image sensors; parallel processing; visual perception; 100 pixel; 10000 pixel; Laplacian-Gaussian-like receptive field; analog VLSI; brain parallel visual system; multichip vision system; orientation selection chip; orientation-selective vision system; primary visual cortex higher order cells; silicon retina; simple cell feed-forward model; simple cell orientation selective response; visual system hierarchical architecture; Aggregates; Brain modeling; Feedforward systems; Image communication; Machine vision; Retina; Silicon; Spatial resolution; Very large scale integration; Visual system;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on
  • Print_ISBN
    0-7803-8834-8
  • Type

    conf

  • DOI
    10.1109/ISCAS.2005.1464987
  • Filename
    1464987