• DocumentCode
    3544153
  • Title

    Quantifying design productivity: an effort distribution analysis

  • Author

    Joshi, Makarand ; Kobayashi, Hideaki

  • Author_Institution
    Dept. of Electr. & Comput. Eng., South Carolina Univ., Columbia, SC, USA
  • fYear
    1995
  • fDate
    18-22 Sep 1995
  • Firstpage
    476
  • Lastpage
    481
  • Abstract
    This paper presents basic process models for textual and graphical HDL-based design. The models are used to measure effort (time) required for various design activities, with an aim to quantify design productivity. Effort-distribution in man-minutes is used as a parameter to evaluate design productivity. Design quality, defined as a probability that the design meets its specifications, is plotted for various design activities. We also discuss the resources that are essential to perform each design activity. These experiments demonstrate that “effort-distribution analysis” is useful for real life HDL-based design projects
  • Keywords
    hardware description languages; human resource management; logic CAD; logic design; ISO 9000; design productivity quantification; design quality; design resources; effort distribution analysis; effort-distribution; effort-distribution analysis; graphical HDL-based design; human interaction; textual HDL; Costs; Hardware design languages; Humans; Logic; Process design; Productivity; Signal synthesis; Testing; Time measurement; Timing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference, 1995, with EURO-VHDL, Proceedings EURO-DAC '95., European
  • Conference_Location
    Brighton
  • Print_ISBN
    0-8186-7156-4
  • Type

    conf

  • DOI
    10.1109/EURDAC.1995.527447
  • Filename
    527447