Title :
Impact of random telegraph noise on CMOS logic delay uncertainty under low voltage operation
Author :
Matsumoto, Tad ; Kobayashi, Kaoru ; Onodera, Hidetoshi
Author_Institution :
Dept. of Commun. & Comput. Eng., Kyoto Univ., Kyoto, Japan
Abstract :
Statistical nature of RTN-induced delay fluctuation is described by measuring 2,520 ROs fabricated in a commercial 40 nm CMOS technology. Small number of samples have a large RTN-induced delay fluctuation. RTN-induced delay fluctuation becomes as much as 10.4% of nominal oscillation frequency under low supply voltage (0.65V). By slightly increasing the transistor size, more than 50% reduction of frequency uncertainty can be achieved under 0.75V operation. The impact of the parameters that can be changed by circuit designers is clarified in view of RTN-induced CMOS logic delay uncertainty.
Keywords :
CMOS logic circuits; delay circuits; CMOS logic delay uncertainty; RTN-induced delay fluctuation; random telegraph noise; size 40 nm; statistical nature; voltage 0.65 V; voltage 0.75 V; CMOS integrated circuits; Delay; Frequency measurement; Oscillators; Substrates; Temperature measurement; Transistors;
Conference_Titel :
Electron Devices Meeting (IEDM), 2012 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4673-4872-0
Electronic_ISBN :
0163-1918
DOI :
10.1109/IEDM.2012.6479104