Title :
High performance adder cell for low power pipelined multiplier
Author_Institution :
EDA Lab., City Univ. of Hong Kong, Kowloon, Hong Kong
Abstract :
A high performance adder structure has been designed with a 0.5 microns n-well CMOS technology. The proposed circuit can operate well at 500 MHz with 5 V supply and 330 MHz with 3 V supply. It has better circuit performances in terms of power consumption, speed and area efficiency compared with Complementary Pass Transistor logic and Differential Cascode Voltage Switch logic. The initial latency of a n-bit pipelined multiplication can be reduced to n from 2n with a two bits adder cell using the proposed circuit. It is suitable for low power low voltage pipelined multiplier implementation
Keywords :
CMOS logic circuits; adders; logic design; multiplying circuits; pipeline arithmetic; 0.5 micron; 3 to 5 V; 330 to 500 MHz; LV pipelined multiplier implementation; area efficiency; high performance adder cell; low power multiplier; low voltage multiplier; n-well CMOS technology; power consumption; Adders; CMOS logic circuits; CMOS technology; Circuit optimization; Degradation; Energy consumption; Inverters; Logic circuits; Low voltage; Switches;
Conference_Titel :
Circuits and Systems, 1996. ISCAS '96., Connecting the World., 1996 IEEE International Symposium on
Conference_Location :
Atlanta, GA
Print_ISBN :
0-7803-3073-0
DOI :
10.1109/ISCAS.1996.541900
