Title :
Biasing techniques for subthreshold MOS resistive grids
Author :
Wee, Keng Hoong ; Sit, Ji-Jon ; Sarpeshkar, Rahul
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA
Abstract :
A classic resistive network implemented using MOS transistors suffers from nonlinearity in the subthreshold exponential parameter κ that arises due to varying VGB and VBS. We show two biasing techniques that alleviate these effects. The first technique always uses transistors with constant gate-to-bulk voltage. The second technique uses a novel bulk-to-source biasing scheme to ensure zero bulk-to-source voltage. We propose a PMOS spatial filtering circuit that employs this scheme to extend the range of linearity of subthreshold resistive networks. Measured experimental results from a 1.5um CMOS process show that our spatial filtering circuit has less than 5% variation in space-constant over a measured 94dB (100fA-5nA) dynamic range as opposed to a conventional spatial filtering circuit, which for the same variation has a measured dynamic range of less than 80dB (100fA-1nA). Our techniques should be useful in translinear MOS circuits where linear operation over a wide dynamic range of input currents is important.
Keywords :
CMOS integrated circuits; MOSFET; spatial filters; MOS transistors; PMOS spatial filtering circuit; bulk-to-source biasing scheme; bulk-to-source voltage; constant gate-to-bulk voltage; nonlinearity; resistive network; subthreshold MOS resistive grids; subthreshold exponential parameter; translinear MOS circuits; Circuits; Computer science; Dynamic range; Filtering; Linearity; MOSFETs; Resistors; Silicon; Spatial filters; Voltage;
Conference_Titel :
Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on
Print_ISBN :
0-7803-8834-8
DOI :
10.1109/ISCAS.2005.1465049