Implementation of a digital phase-locked loop using CORDIC algorithm

A phase-locked loop is a control system that has already been in use for a long time for generating an output signal which is synchronized in frequency and phase to an input signal. The superior noise immunity and tracking capability of phase-locked loop makes it very attractive device in many applications, e.g. clock and data separation, FSK demodulator and doppler recovery. The objective of this paper is to propose a novel digital phase-locked loop structure which can be easily implemented using the CORDIC algorithm. Implementation of those phase-locked loop structures using the CORDIC algorithm makes VLSI recitations very feasible. CORDIC algorithm is also easily pipelined in order to achieve high-performance in computation systems