Title :
Thinning, stacking, and TSV proximity effects for Poly and High-K/Metal Gate CMOS devices in an advanced 3D integration process
Author :
Lo, Tank ; Chen, Mayee F. ; Jan, S.B. ; Tsai, W.C. ; Tseng, Y.C. ; Lin, C.S. ; Chiu, T.J. ; Lu, W.S. ; Teng, H.A. ; Chen, S.M. ; Hou, S.Y. ; Jeng, S.P. ; Yu, Cody Hao
Author_Institution :
R&D, Taiwan Semicond. Manuf. Co., Ltd., Hsinchu, Taiwan
Abstract :
An advanced 3D integration process featuring through silicon via (TSV) and chip-on-wafer (CoW) technologies has been demonstrated. Using this 3D process, Poly and High-K/Metal Gate (HKMG) CMOS wafers have been successfully thinned and stacked, showing little to no degradation in the process. The effect of TSV induced mechanical stress on ΔIdsat for HKMG is found to be smaller as compared to Poly Gate devices for the same channel length (ΔIdsat ratio of HKMG to Poly is ~0.3 and ~0.5 for PMOS and NMOS, respectively). In addition, we show that ΔIdsat for HKMG device is proportional to TSV diameter square, independent of TSV orientation, device polarity, and device distance from TSV.
Keywords :
CMOS integrated circuits; semiconductor device manufacture; stacking; three-dimensional integrated circuits; ΔIdsat; CoW technologies; HKMG CMOS wafers; HKMG device; TSV diameter square; TSV induced mechanical stress; TSV orientation; TSV proximity effects; TSV technologies; advanced 3D integration process; channel length; chip-on-wafer technologies; device distance; device polarity; high-K-metal gate CMOS devices; poly-metal gate CMOS; stacking effects; thinning effects; through silicon via technologies; CMOS integrated circuits; Logic gates; MOS devices; Performance evaluation; Stacking; Stress; Through-silicon vias;
Conference_Titel :
Electron Devices Meeting (IEDM), 2012 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4673-4872-0
Electronic_ISBN :
0163-1918
DOI :
10.1109/IEDM.2012.6479158
