A cost-effective morphological filter architecture

This paper proposes a new VLSI architecture for morphological filters and presents its design and implementation. The proposed architecture can significantly reduce the hardware cost by using a feedback loop path and a decoder/encoder pair comparator. The feedback loop path can reuse partial results and the decoder/encoder pair comparator can reduce the gate delay and the gate count especially when the size of the structuring element increases. In addition, the proposed architecture requires fewer number of operations and can be easily extended for larger size morphological operations. We fabricated the actual chip using the 0.8 μm Samsung^TM SOG cell library (KG60K) and the total number of gates is only 2,667. The proposed morphological filter chip has been actually fabricated and is running at 30 MHz that meets real-time image processing requirements of the ITU-R BT. 601 standard