How to efficiently build VHDL testbenches

The paper describes a reuse methodology, which eases the creation of testbenches. In our approach, beside providing a library of precompiled basic functions and entities, the designer receives descriptions of complete test concepts (e.g, macro-oriented stimulation or comparison of two simulations), including a source code example, called template, and a guide for the adaption of the template to her/his application. Furthermore, an overall guide for the whole validation phase is provided. The paper describes the typical structure of a testbench, presents the implementations of major objects, and demonstrates the method of user guidance. Further, the global test concept for reuse components is demonstrated