Architecture of out of order TURBO51 embedded microprocessor

In this paper, it is firstly give the background and the considerations to follow this technological roadmap of design the TURBO51. It then introduces the architecture design of instruction out of order pipeline, includes the branch prediction, dynamical execution and memory management. The various test patterns in running real applications indicates that TURBO51 has one-time successful taped out and under the same work clock frequency, it outperforms over 20 times faster than its traditional counterpart. However, owing to no implementation of a full data-cache and the three-layer-memory-hierarchy, the performance over 100 MHz is supposed to be hampered and automatic test vector generation in verification needs further enhancement.