DocumentCode
3545314
Title
Well-defined design procedure for a three-stage CMOS OTA
Author
Mita, R. ; Palumbo, G. ; Pennisi, S.
Author_Institution
Dipt. di Ingegneria Elettrica Elettronica e dei Sistemi, Catania Univ., Italy
fYear
2005
fDate
23-26 May 2005
Firstpage
2579
Abstract
A simple and well-defined design procedure for a three-stage CMOS OTA is presented in this paper. The approach is suited for a pencil-and-paper design and yields accurate performance optimization without introducing unnecessary circuit constraints. Simulations on a circuit implemented in a 0.35-μm technology closely agree the results expected.
Keywords
CMOS analogue integrated circuits; circuit optimisation; circuit simulation; integrated circuit design; operational amplifiers; 0.35 micron; circuit constraints; circuit technology; design procedure; pencil-and-paper design; performance optimization; simulation; three-stage CMOS OTA; CMOS technology; Circuit simulation; Circuit topology; Computational modeling; Computer simulation; MOSFETs; Mirrors; Optimization; Transconductance; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on
Print_ISBN
0-7803-8834-8
Type
conf
DOI
10.1109/ISCAS.2005.1465153
Filename
1465153
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