A low spur fractional-N frequency synthesizer architecture

A new architecture of a fractional-N phase-locked loop (PLL) frequency synthesizer is presented in this paper. The unique feature of the proposed frequency synthesizer is a loop filter with a discrete time comb filter which allows for the efficient suppression of fractional spurs. The proposed loop filter architecture can be efficiently implemented using switched capacitor techniques. The benefits of this approach are a low power frequency synthesizer design with low spur levels. An analysis of the fractional spurs in the fractional-N frequency synthesizers is also presented.