Title :
An efficient dual-interpolator architecture for sub-pixel motion estimation
Author :
Wang, Yueh-Yi ; Tsai, Chun-Jen
Author_Institution :
Dept. of Comput. Sci. & Inf. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Abstract :
The new generation video codecs typically adopt a sophisticated interpolation filter for sub-pixel motion estimation (ME). For embedded applications, it is crucial to reduce both the memory requirement and the computational complexity for sub-pixel ME. The paper´s key observation is that the interpolation filter for motion estimation and the filter for coding do not have to be the same. By adopting a simpler on-the-fly interpolation filter during the ME process and a standard-compliant filter for coding, both memory and complexity can be reduced with very little coding performance degradation. Since Hadamard transformed-SAD (sum of absolute differences) is often used in high quality codecs as a better matching measure, we further show that the ME interpolation filer can be combined with the Hadamard transform for efficient VLSI implementation. Initial results show a very promising performance by the proposed system.
Keywords :
Hadamard transforms; VLSI; computational complexity; embedded systems; filtering theory; interpolation; motion estimation; video codecs; video coding; Hadamard transform; VLSI; computational complexity; dual-interpolator architecture; embedded applications; interpolation filter; memory requirement; subpixel motion estimation; sum of absolute differences; video codecs; video coding filter; Computational complexity; Computer architecture; Degradation; Error correction; Error correction codes; Filters; Interpolation; Motion estimation; Very large scale integration; Video codecs;
Conference_Titel :
Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on
Print_ISBN :
0-7803-8834-8
DOI :
10.1109/ISCAS.2005.1465235