A unique section overhead processor for STM-64

Author

Lee, Tae-Hee ; Cho, Jae-II ; Ko, Jeong-Hoon

Author_Institution

Electron. & Telecommun. Res. Inst., Taejon, South Korea

fYear

1997

fDate

7-10 Sep 1997

Firstpage

155

Lastpage

159

Abstract

A Unique CMOS Section Overhead (SOH) processor has been designed for use in 10 Gbit/s SDH-based optical transmission system. A uniquely structured chip makes it possible to use parallel processing of STM-64 SOH at low speed with four identical chips. The features supported by the chips include STM-64 SOH insertion and extraction including Regenerator Section Trace (RST), frame alignment word insertion, alarm detection and generation, and performance monitoring. This paper introduces a novel parallel circuit design methodology for processing STM-64 SOH and describes the unique architecture, implementation and experimental test results of the chip, SOH processor. This paper also presents the implementation methodology of RST using CRC-7 polynomial algorithm

Keywords

CMOS digital integrated circuits; application specific integrated circuits; digital communication; microprocessor chips; optical communication equipment; parallel architectures; synchronous digital hierarchy; 10 Gbit/s; CMOS; CRC-7 polynomial algorithm; SDH-based optical transmission system; STM-64; alarm detection; frame alignment word insertion; parallel circuit design methodology; parallel processing; performance monitoring; regenerator section trace; section overhead processor; Application specific integrated circuits; Asynchronous transfer mode; CMOS process; Circuit synthesis; Circuit testing; Gallium arsenide; Monitoring; Polynomials; Signal processing; Synchronous digital hierarchy;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Conference and Exhibit, 1997. Proceedings., Tenth Annual IEEE International

Conference_Location

Portland, OR

ISSN

1063-0988

Print_ISBN

0-7803-4283-6

Type

conf

DOI

10.1109/ASIC.1997.616997

Filename

616997