Analysis of clock jitter error in multibit continuous-time ΣΔ modulators with NRZ feedback waveform

This paper presents a detailed study of the clock jitter error in multibit continuous-time ΣΔ modulators with non-return-to-zero feedback waveform. Closed-form expressions are derived for the in-band error power and the signal-to-noise ratio showing that the jitter-induced noise can be separated into two main components: one depending on the modulator loop filter and the other one due to the input signal. The latter, not considered in previous approaches, allows us to accurately predict the signal-to-noise ratio degradation and to optimize the modulator performance in terms of jitter insensitivity. Moreover, the use of state-space formulation makes the analysis quite general and applicable to either cascaded or single-loop architectures. Time-domain simulations of several modulators are shown to validate the presented approach.