A power-driven multiplication instruction-set design method for ASIPs

This paper presents a novel power-driven multiplication instruction-set design method for ASIP (application specific instruction-set processors). Based on a dual-and-configurable-multiplier structure, our proposed method devises a multiplication instruction-set for low-power ASIP. Our method exploits the execution sequences of multiplication instructions and effective bit-widths of variables to reduce power consumed by redundant multiplication bits while minimizing the multiplication execution time. Experimental results on a set of DSP programs demonstrate that our proposed method achieves significant power reduction (up to 18.98%) and execution time improvement (up to 10.51%) with 18% area overhead.