DocumentCode
3546458
Title
Elimination of sign precomputation in flat CORDIC
Author
Suchitra, S. ; Sukthankar, S. ; Srikanthan, T. ; Clarke, C.T.
Author_Institution
Center for High Performance Embedded Syst., Nanyang Technol. Univ., Singapore
fYear
2005
fDate
23-26 May 2005
Firstpage
3319
Abstract
Flat CORDIC, which was originally proposed to overcome the performance limitations of iterative CORDIC, suffers from the bottleneck of sign prediction prior to the start of computations. Also, this sign precomputation unit has poor scalability. We propose a method for totally eliminating this need for sign precomputation, by directly inferring the directions of rotation from the bipolar representation of the input angle. The proposed engine was implemented using 0.35 micron technology and the resource utilization is reported.
Keywords
digital arithmetic; digital signal processing chips; signal processing; bipolar representation; flat CORDIC; performance; rotation directions; sign precomputation; Embedded computing; Embedded system; Engines; Equations; Hardware; High performance computing; Iterative algorithms; Logic; Scalability; Writing;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on
Print_ISBN
0-7803-8834-8
Type
conf
DOI
10.1109/ISCAS.2005.1465338
Filename
1465338
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