Title :
I/O impedance matching algorithm for high-performance ASICs
Author :
Zuchowski, Paul S. ; Panner, Jeannie H. ; Stout, Douglas W. ; Adam, Janice M. ; Chan, Francis ; Dunn, Paul E. ; Huber, Andrew D. ; Oler, Joseph J.
Author_Institution :
Microelectron. Div., IBM Corp., Essex Junction, VT, USA
Abstract :
This paper discusses a design style that utilizes an area array of flip-chip solder bump connections, I/O circuit designs that implement a programmable impedance matching algorithm, and a design system that must utilize these features during chip layout, chip checking, and release to manufacturing. Results from a recent test chip are also given
Keywords :
application specific integrated circuits; circuit layout CAD; flip-chip devices; impedance matching; integrated circuit interconnections; integrated circuit layout; I/O impedance matching algorithm; area array; chip layout; design style; flip-chip solder bump connections; high-performance ASICs; programmable impedance matching algorithm; Algorithm design and analysis; Application specific integrated circuits; Driver circuits; Electromigration; Electrostatic discharge; Impedance matching; Logic; Resistors; Thermal resistance; Wire;
Conference_Titel :
ASIC Conference and Exhibit, 1997. Proceedings., Tenth Annual IEEE International
Conference_Location :
Portland, OR
Print_ISBN :
0-7803-4283-6
DOI :
10.1109/ASIC.1997.617019
