An efficient direct 2-D transform coding IP design for MPEG-4 AVC/H.264

This paper proposes an efficient direct 2D transform coding IP design for MPEG-4 AVC/H.264. The proposed direct 2D transform coding design eliminates the data transposition registers to greatly increase the data processing rate and reduce the hardware cost. When comparing the proposed design with the existing designs, the proposed design has over 90% higher hardware efficiency through the measure of DTUA (data throughput per unit area) for computing the multi-transform in MPEG-4 AVC/H.264. By using a 0.18-μm CMOS technology, the optimum operating clock frequency of the proposed multi-transform design is 100 MHz, which achieves 800 Mpixels/sec data throughput rate with an area cost of 6482 gates. Moreover, the proposed design balances the I/O data rate and processing rate through an interlaced I/O schedule.