DocumentCode :
3547962
Title :
Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference 2005 (IEEE Cat. No.05EX950C)
Volume :
1
fYear :
2005
fDate :
21-21 Jan. 2005
Abstract :
The following topics are dealt with: CAD for microarchitecture designs; design for manufacturability; tree construction and buffering; network-on-chip; integrated circuit testing; design for testability; clocks; power grid analysis; thermal analysis; network routing; integrated circuit interconnections; system level modeling; embedded software; TCAD; RF/analog circuits; logic synthesis; system level architecture design; formal verification; integrated circuit placement; security processor design; design optimization; high-performance digital circuits; floorplanning; SAT technology; interconnect modeling; high-level synthesis; low-power electronics; digital signal processing; FPGA; RF circuit design; embedded systems; real-time systems; crosstalk noise avoidance; power/ground network optimization; analog circuit design; SRAM; and system-on-chip.
Keywords :
SRAM chips; analogue circuits; circuit CAD; circuit optimisation; clocks; design for manufacture; design for testability; digital circuits; electronic design automation; formal verification; high level synthesis; integrated circuit design; integrated circuit interconnections; integrated circuit layout; integrated circuit modelling; integrated circuit testing; logic design; low-power electronics; microprocessor chips; radiofrequency integrated circuits; system-on-chip; technology CAD (electronics); CAD; FPGA; RF circuit design; SRAM; TCAD; analog circuit design; buffering; clocks; crosstalk noise avoidance; design automation; design for manufacturability; design for testability; design optimization; digital signal processing; embedded software; embedded system; floorplanning; formal verification; high-level synthesis; high-performance digital circuits; integrated circuit interconnections; integrated circuit placement; integrated circuit testing; interconnect modeling; logic synthesis; low-power electronics; microarchitecture designs; network routing; network-on-chip; power grid analysis; power/ground network optimization; real-time system; satisfiability; security processor design; system level architecture design; system level modeling; thermal analysis; tree construction;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference, 2005. Proceedings of the ASP-DAC 2005. Asia and South Pacific
Conference_Location :
Shanghai
Print_ISBN :
0-7803-8736-8
Type :
conf
DOI :
10.1109/ASPDAC.2005.1466090
Filename :
1466090
Link To Document :
بازگشت