Multigigabit balanced add-select-register-compare viterbi decoders architecture in 60 GHz WPAN

Author

Bo Gao ; Zhenyu Xiao ; Zhen Chen ; Depeng Jin ; Lieguang Zeng

Author_Institution

Dept. of Electron. Eng., Tsinghua Univ., Beijing, China

fYear

2013

fDate

29-31 Aug. 2013

Firstpage

531

Lastpage

535

Abstract

In this paper, a novel lower-power multigigabit Viterbi decoder architecture is proposed for 60 GHz wireless personal-area network (WPAN) systems. Since add-compare-select (ACS) computation is the main bottleneck in decoding speed of Viterbi decoders, a balanced add-select-register-compare (BASIC) architecture is put forward to reduce critical path of ACS with low complexity. This work develops an 8-parallel BASIC Viterbi decoder for IEEE 802.15.3c standard to accomplish high-throughput and low-power goals. Based on synthesized results in 0.13 μm CMOS technology, the proposed decoder achieves up to 4 Gb/s throughput with energy efficiency 0.104 nJ/bit at 1.2 V.

Keywords

CMOS integrated circuits; IEEE standards; MMIC; Viterbi decoding; energy conservation; network coding; personal area networks; ACS computation; CMOS technology; IEEE 802.1S.3c standard; WPAN; add-compare select; balanced add-select register compare; energy efficiency; frequency 60 GHz; multigigabit BASIC; parallel BASIC Viterbi decoder architecture; size 0.13 mum; voltage 1.2 V; wireless personal area network; CMOS integrated circuits; CMOS technology; Computer architecture; Decoding; Educational institutions; Throughput; Viterbi algorithm; 60 GHz; Viterbi decoders; WPAN; balanced add-select-register-compare (BASIC); multigigabit;

fLanguage

English

Publisher

ieee

Conference_Titel

Communications (APCC), 2013 19th Asia-Pacific Conference on

Conference_Location

Denpasar

Print_ISBN

978-1-4673-6048-7

Type

conf

DOI

10.1109/APCC.2013.6766005

Filename

6766005