Oscillation ring based interconnect test scheme for SoC

Author

Li, Kathei-Ine Shu-Min ; Lee, Chug Len ; Su, Chauchin ; Chen, Jwu E.

Author_Institution

Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan

Volume

1

fYear

2005

fDate

18-21 Jan. 2005

Firstpage

184

Abstract

We propose a novel oscillation ring (OR) test architecture for testing interconnects in SoC. In addition to stuck-at and open faults, this scheme can detect delay faults and crosstalk glitches. IEEE P1500 wrapper cells are modified. An efficient ring-generation algorithm is proposed to construct ORs based on a graph model. Experimental results on MCNC benchmark circuits show the feasibility of the scheme and the effectiveness of the algorithm. Our method achieves 100% fault coverage with a small number of tests.

Keywords

fault diagnosis; integrated circuit interconnections; integrated circuit testing; logic testing; system-on-chip; IEEE P1500 wrapper cells; crosstalk glitches; delay fault; graph model; interconnect test scheme; open fault; oscillation ring test architecture; ring generation algorithm; stuck-at fault; system on chip; Circuit faults; Circuit testing; Counting circuits; Crosstalk; Delay; Electrical fault detection; Electronic mail; Fault detection; Integrated circuit interconnections; Logic testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 2005. Proceedings of the ASP-DAC 2005. Asia and South Pacific

Print_ISBN

0-7803-8736-8

Type

conf

DOI

10.1109/ASPDAC.2005.1466154

Filename

1466154