Title :
Test generation for synchronous sequential circuits using multiple observation times
Author :
Pomeranz, I. ; Reddy, S.M.
Author_Institution :
Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
Abstract :
The test generation problem for synchronous sequential circuits is considered in the case where hardware reset is not available. The observations which form the motivation for the work are given. On the basis of the observations, the use of multiple fault free responses as well as multiple time units for fault detection is suggested. Application to gate level synchronous sequential circuits is then considered. Experimental results are given to support the claim that a small number of observation times is required, and that a small number of fault free responses need be stored for every fault. 100% fault efficiency is achieved.<>
Keywords :
fault location; logic testing; sequential circuits; fault detection; hardware reset; multiple fault free responses; multiple observation times; multiple time units; synchronous sequential circuits; test generation; Circuit faults; Circuit testing; Clocks; Electrical fault detection; Fault detection; Hardware; Sequential analysis; Sequential circuits; Synchronization; Synchronous generators;
Conference_Titel :
Fault-Tolerant Computing, 1991. FTCS-21. Digest of Papers., Twenty-First International Symposium
Conference_Location :
Montreal, Quebec, Canada
Print_ISBN :
0-8186-2150-8
DOI :
10.1109/FTCS.1991.146632