Adiabatic CMOS gate and adiabatic circuit design for low-power applications

The methodology for designing adiabatic circuits employing two-phase power clock, is investigated. First, algebraic expressions for and properties of power-clocked signals are discussed. Then the design of adiabatic gates based on AC power supply and CMOS transmission gates is analyzed. On this basis, basic rules for the design of adiabatic circuits are proposed, and a design example of an adiabatic full adder is demonstrated. SPICE simulations using a trapezoidal power-clock demonstrate that the designed adiabatic circuits have a correct logic function and ultra low-power characteristics.