Instruction scheduling of VLIW architectures for balanced power consumption

An instruction word in VLIW (very long instruction word) processors consists of a variable number of individual instructions. Therefore the power consumption variation over time significantly depends on the parallel instruction schedule generated by the compiler. Sharp power variations across time cause power supply noises, degrade chip reliability and accelerate battery exhaustion. This paper proposes a branch and bound algorithm for instruction scheduling of VLIW architectures that effectively minimizing power variation without degrading the speed. Our experimental results demonstrate the efficiency of our algorithm compared with previously presented approaches. Finally, a new rough sets based approach to the instruction-level VLIW power model for this instruction scheduling optimization problem is discussed.