Architecture and performance comparison of a statistic-based lottery arbiter for shared bus on chip

Author

Zhang, Yan

Author_Institution

Shenzhen Graduate Sch., Harbin Inst. of Technol., Guangdong, China

Volume

2

fYear

2005

fDate

18-21 Jan. 2005

Firstpage

1313

Abstract

This paper presents a statistic-based priority strategy for dynamic priority arbiters and its application was investigated for the lottery arbiter. Two set M×M registers are proposed to record the arbitration history. The period of recording arbitration history is programmable. A randomized verification environment is used to do performance comparison for statistic-based and nonstatistic-based arbiters, the results show that the performance is improved when different master´s request pattern is changed dynamically due to different programs running at system on chip and especially when the grants of different master´s requests are correlated.

Keywords

asynchronous circuits; circuit CAD; digital arithmetic; formal verification; integrated circuit design; logic CAD; programmable logic arrays; shift registers; statistical analysis; system-on-chip; M×M registers; arbitration history; dynamic priority arbiters; master requests; nonstatistic-based arbiters; randomized verification environment; shared bus on chip; statistic-based lottery arbiter; statistic-based priority strategy; system on chip; Clocks; History; Monitoring; Performance analysis; Round robin; SDRAM; Signal design; System-on-a-chip; Time division multiple access; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 2005. Proceedings of the ASP-DAC 2005. Asia and South Pacific

Print_ISBN

0-7803-8736-8

Type

conf

DOI

10.1109/ASPDAC.2005.1466585

Filename

1466585