Mobility and CMOS devices/circuits on sub-10nm [110] ultra thin body SOI

Author

Shang, Huiling ; Rubino, J. ; Doris, B. ; Topol, A. ; Sleight, J. ; Cai, J. ; Chang, L. ; Ott, J.A. ; Kedzierski, J. ; Chan, K. ; Shi, L. ; Babich, K. ; Newbury, J. ; Sikorski, E. ; To, B.N. ; Zhang, Y. ; Guarini, K.W. ; Ieong, Meikei

Author_Institution

Res. Div., IBM Semicond. R&D Center, New York, NY, USA

fYear

2005

fDate

14-16 June 2005

Firstpage

78

Lastpage

79

Abstract

For the first time, we show the experimental inversion mobility data on ultra thin [110] SOI substrates for thickness as thin as 6nm. Both electron and hole mobility in ultra thin [110] SOI are evaluated as a function of SOI thickness. In addition, novel processes such as [110] selective epitaxy and extremely thin cobalt disilicide CoSi₂ are developed. Ring oscillators and SRAM cell are demonstrated for the first time on 6nm [110] ultra thin SOI. When compared to ultra thin SOI in (100) substrate, we observe ∼33% drive current enhancement in PFETs at Lg=50nm and ∼1.8X hole mobility enhancement.

Keywords

CMOS integrated circuits; MIS devices; SRAM chips; cobalt compounds; electron mobility; field effect transistors; hole mobility; isolation technology; nanotechnology; oscillators; silicon-on-insulator; CMOS circuit; CMOS device; PFET; SOI thickness; SRAM cell; cobalt disilicide; electron mobility; hole mobility; inversion mobility data; ring oscillator; ultra thin SOI; Charge carrier processes; Circuits; Cobalt; Degradation; Electron mobility; Epitaxial growth; Fabrication; Random access memory; Ring oscillators; Substrates;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2005. Digest of Technical Papers. 2005 Symposium on

Print_ISBN

4-900784-00-1

Type

conf

DOI

10.1109/.2005.1469219

Filename

1469219