Highly scalable and reliable 2-bit/cell SONOS memory transistor beyond 50nm NVM technology using outer sidewall spacer scheme with damascene gate process

Author

Choi, Byung Yong ; Park, Byung-Gook ; Lee, Yong Kyu ; Sung, Suk Kang ; Kim, Tae Yong ; Cho, Eun Suk ; Cho, Hye Jin ; Oh, Chang Woo ; Kim, Sung Hwan ; Kim, Dong Won ; Lee, Choong-Ho ; Park, Donggun

Author_Institution

Sch. of Electr. Eng. & Comput. Sci., Seoul Nat. Univ., South Korea

fYear

2005

fDate

14-16 June 2005

Firstpage

118

Lastpage

119

Abstract

We present a 2-bit/cell SONOS memory transistor and investigate its scalability and reliability beyond 50nm NVM technology. This new memory, which is implemented by the damascene gate and our newly developed outer sidewall spacer processes, shows not only stable 2-bit operation but also high reliabilities (>10⁵ endurance and good retention at 150°C) down to 80nm gate length that applies to next-generation NVM technology. In addition, dimensional effect (the lateral distance between two storage nodes) on the memory operation is reported to estimate the ultimate scaling limit of 2-bit/cell SONOS memory transistor.

Keywords

flash memories; semiconductor device reliability; semiconductor-insulator-semiconductor devices; 2-bit/cell SONOS memory transistor; NVM technology; damascene gate process; dimensional effect; outer sidewall spacer scheme; storage nodes; ultimate scaling limit; Computer science; Electron traps; Nonvolatile memory; Research and development; SONOS devices; Scalability; Semiconductor device reliability; Silicon compounds; Space technology; Transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2005. Digest of Technical Papers. 2005 Symposium on

Print_ISBN

4-900784-00-1

Type

conf

DOI

10.1109/.2005.1469235

Filename

1469235