Title :
Flash ETOX™ virtual ground architecture: a future scaling direction
Author :
Koval, Randy J. ; Bhachawat, V. ; Chang, C. ; Hajra, M. ; Kencke, D. ; Kim, Y. ; Kuo, C. ; Parent, T. ; Wei, M. ; Woo, B.J. ; Fazio, A.
Author_Institution :
Intel Corp., Santa Clara, CA, USA
Abstract :
A 65nm generation virtual ground (VG) ETOX™ flash memory process capable of MLC operation and relying on a conventional channel hot electron program and F-N tunneling channel erase has been demonstrated. Several key process elements were successfully integrated to achieve functional test structures with 0.0315 μm2 cell size. The significant area scaling benefit was achieved in large part by replacing the drain contacts and metal interconnect in the array with a buried bitline diffusion implant. In addition to achieving the significant reduction in cell size, such an approach offers several important technological advantages compared to the conventional approach used by its predecessor technology and provides a promising path for continued future scaling of flash memories.
Keywords :
flash memories; hot carriers; integrated circuit interconnections; memory architecture; nanotechnology; semiconductor process modelling; tunnelling; 65 nm; F-N tunneling channel erase; MLC operation; area scaling; buried bitline diffusion implant; conventional channel hot electron program; drain contact; flash ETOX™ virtual ground architecture; flash memory process; metal interconnect; Educational institutions; Electrons; Flash memory; Implants; Nonvolatile memory; Oxidation; Scalability; Silicon; Testing; Tunneling;
Conference_Titel :
VLSI Technology, 2005. Digest of Technical Papers. 2005 Symposium on
Print_ISBN :
4-900784-00-1
DOI :
10.1109/.2005.1469268